1. Field of the Invention
The present invention generally relates to the manufacturing of bipolar devices. It applies to the manufacturing of bipolar transistors in pure bipolar technology or in mixed bipolar MOS (BICMOS) technology.
2. Discussion of the Related Art
Manufacturing the base-emitter junctions of bipolar transistors raises different problems. It is in particular desirable to have self-aligned manufacturing processes to reduce the dimensions of the devices.
It is also desirable not to implant the base, which inevitably creates gaussian doping profiles. The base is ideally formed by a doped epitaxial deposition.
It is also desirable to minimize the access resistance to the base (base resistance) and to improve the frequency response of the transistors. For this purpose, it has in particular been provided to use as a base a silicon-germanium layer. However, the use of germanium, although considerably improving the access resistance of a bipolar transistor and the transit time through the base, raises implementation problems. It is difficult to bring this germanium by an implantation into a silicon layer, and such a layer does not withstand high temperatures.
An object of the present invention thus is to provide a novel method of manufacturing bipolar transistors enabling formation of base-emitter junctions in a self-aligned way.
Another object of the present invention is to provide such a method that reduces or minimizes the base resistance of the transistors.
Another object of the present invention is to provide such a method that is compatible with the use of a silicon-germanium base region.
To achieve these and other objects, the present invention provides a method of manufacturing the emitter-base junction of a bipolar transistor on an active silicon region of a first conductivity type delimited by a trench filled with a field insulation material, the assembly being covered with a first insulating layer. The method includes the steps of etching the first insulating layer to expose the surface of the active region; etching the surface of the active region across a given height; forming first and second very heavily-doped silicon spacers of the second conductivity type at the internal periphery of the abrupt protrusions respectively resulting from the etching of the first insulating layer and from the etching of the active region; depositing by epitaxy a doped base layer of the second conductivity type; forming a third spacer in an insulating material at the internal periphery of a protrusion of the base layer corresponding to the first spacer; depositing a heavily-doped silicon emitter layer of the first conductivity type; and performing a chem-mech polishing, by using the first layer and the third spacer as stops.
According to an embodiment of the present invention, the method includes, for the etching of the active region, the steps of depositing a silicon layer of a predetermined thickness on the first insulating layer; masking and removing the silicon layer and the first insulating layer above the active area; and selectively etching the silicon with detection and etch stop when the first insulating layer is reached.
According to an embodiment of the present invention, the forming of the first and second spacers is followed by an overetching of the active region.
According to an embodiment of the present invention, the first insulating layer is a multilayer formed of a silicon oxide layer and of a silicon nitride layer.
According to an embodiment of the present invention, the first and second spacers are made of doped polysilicon of the second conductivity type.
According to an embodiment of the present invention, at least the first spacer is made of single-crystal silicon.
According to an embodiment of the present invention, the base layer is formed of silicon and germanium.
According to an embodiment of the present invention, the germanium gradient and the gradient of dopant of the first conductivity type in the base layer are such that the maximum germanium concentration and the maximum dopant concentration are respectively close to the interface with the active region and to the interface with the emitter region.
According to an embodiment of the present invention, the third spacer is made of silicon oxide.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.